This invention relates to charge pumps that are used in PLLs (Phase Locked Loops) for applications such as frequency synthesis/clock generation.
In the field of this invention it is known that for Fractional N (FRAC-N) PLL arrangements, linearity of the associated charge pump is a key requirement. A major problem in the circuit design of such charge pumps is achieving a required level of linearity around the xe2x80x9clockxe2x80x9d condition.
The nature of PLL modulation during the xe2x80x9clockxe2x80x9d condition requires that extra charge is added or taken out of the loop filter, the charge being proportionate to the modulation.
In the case of a mobile cellular telecommunications device arranged to transmit using a direct digital modulation technique and using a PLL as described above, the tuning line voltage of a Voltage Controlled Oscillator (VCO) of the device is modulated, which in turn causes Frequency Modulation (FM) on a transmit (or TX) output of the device. Non-linearity of the PLL in this arrangement leads to unwanted noise at the TX output.
The modulation rate can vary in steps as high as the period of the highest expected frequency (for example xcx9c1 ns for a GSMxe2x80x94Global System for Mobile telecommunicationxe2x80x94device) over a range of a number of periods (dictated by the modulation) of the lowest expected frequency around the Integer xe2x80x9clockxe2x80x9d condition.
Hence the overall charge transferred to a loop filter of the PLL over these conditions has to be substantially linear so that the FM modulation of the VCO output in closed loop is proportionate to the data being transmitted by direct digital modulation technique.
Furthermore it is known that in the locked condition an intentional leakage current can be added to the source current of the loop filter such that a xe2x80x98downxe2x80x99 portion of the charge pump is toggled during the xe2x80x9clockxe2x80x9d condition to compensate or to sink current equal to the sourced current over one reference period. Therefore the linearity depends on the constant sourced current and the pulsed xe2x80x98downxe2x80x99 current.
The relatively high currents (1.26 mA) required to achieve the gain of the Phase Frequency Detector for a GSM application are typically provided by large Field Effect Transistors (FETs) with associated parasitic capacitances, and these parasitics cause unwanted charge injection and clock feed-through when switched, resulting in non-linearity around the xe2x80x9clockxe2x80x9d condition as well as longer acquisition time with increased power dissipation.
xe2x80x9cA NEW LOW VOLTAGE CHARGE PUMP CIRCUIT FOR PLLxe2x80x9d, by Robert C. Chang and Lung-Chih Kuo, ISCAS 2000xe2x80x94IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland, describes a 1.5V application using Wide Swing Current Mirrors and current steering techniques to tackle these noise problems.
However, this approach has the disadvantages that it provides a limited output impedance, operates with a limited supply voltage and is relatively complex, having two stages. In the context of cellular transceiver equipment, the charge pump must be able to work over a voltage range as large as possible, and a suitably large supply voltage is required. Furthermore in such an application a PLL arrangement must be relatively simple and inexpensive.
A need therefore exists for a PLL arrangement, charge pump, method and mobile transceiver wherein the abovementioned disadvantage(s) may be alleviated.
In accordance with a first aspect of the present invention there is provided a charge pump as claimed in claim 1.
In accordance with a second aspect of the present invention there is provided a PLL arrangement as claimed in claim 2.
In accordance with a third aspect of the present invention there is provided a mobile transceiver as claimed in claim 3.
In accordance with a fourth aspect of the present invention there is provided a method as claimed in claim 5.
Preferably the charge pump further comprises first and second transistors coupled in cascode arrangement between the current source circuit and the current sink circuit.
The current source circuit and the current sink circuit preferably each have switching transistors arranged to be switched via their source electrodes. Preferably the current sink circuit includes a positive feedback arrangement.
The phase-locked-loop arrangement is preferably provided for a cellular transceiver. Preferably the cellular transceiver is a GSM device. Alternatively the cellular transceiver is a xe2x80x98post-2Gxe2x80x99 generation device.
In this way bias currents of the arrangement are mirrored according to the output current required, leading to improved transient times and reduced phase noise.